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Memory Centric Research Projects

Memory-Centric Research Projects

Virginia Tech's UPWARDS Pillar 4 contributions span six peer-reviewed publications on in-memory computing, MRAM- and SRAM-based compute-in-memory, hyperdimensional architectures, and binary neural network accelerators. The sections below summarize each project's design specifications, research contributions, and representative figures, drawn from the Year 4 NSF annual report deck. A full reference list with publication links appears at the bottom of the page.

NMPHDC: A 12 nm Reconfigurable Multi-port SRAM based Near-Memory Hyperdimensional Computing Architecture

Design Specifications

  • Technology: GF 12LP FinFET
  • Memory Technologies: Multiport SRAM
  • Power and Area: 19.7 mW, 1.25 mm. square.
  • Supported Dimension: 256/512/1024
  • Operating Frequency: 100 MHz
  • Training Methodology: On-Chip

Research Contributions

  • A reconfigurable near-memory hyperdimensional computing architecture.
  • On-chip random number generator for secured training, and incremental learning.
  • Key accuracies: ECG5000 93.33%, MNIST 72.62%, ISOLET 75.18%.
Fig: Top NMPHDC Architecture.
Fig: Multi-port SRAM organization.

An In-Memory Computing Architecture Utilizing Energy-Efficient VGSOT MRAM Device

Design Specifications

  • Technology: GF 22 FDSOI
  • Memory Technologies: Voltage-gated spin orbit torque (VGSOT) Magnetic Random Access Memory (MRAM)
  • Bit-Cell Type: 4 transistor 1 resistor (4T1R)
  • Memory Capacity: 1.57 Mb
  • Memory Type: Non-volatile
  • Neural Network: Binary Neural Network (BNN)
  • Accuracy: MNIST 95.04%, FMNIST 84.59%.

Research Contributions

  • A 2-Mb IMC architecture using an emerging VGSOT MRAM device in 22-nm FDSOI technology.
  • supports non-volatile storage, logic operations such as AND, NAND, OR, and NOR, and in-memory dot products for BNNs.
  • A compact 3T1R bit-cell is used with a dual word-line decoder and a separately precharged sense amplifier.
  • Implementation of binary neural network (BNN) for different edge applications.
Fig: VGSOT device and 4T1R bit-cell
Fig: 1.57-Mb VGSOT MRAM architecture

An In-Memory Power Efficient Computing Architecture with Emerging VGSOT MRAM Device

Design Specifications

  • Technology: GF 22 FDSOI
  • Memory Technologies: Voltage-gated spin orbit torque (VGSOT) Magnetic Random Access Memory (MRAM)
  • Bit-Cell Type: 3 transistor 1 resistor (3T1R)
  • Memory Capacity: 2 Mb
  • Memory Type: Non-volatile
  • Neural Network: Binary Neural Network (BNN)
  • Accuracy: MNIST 95.04%, FMNIST 84.59%.

Research Contributions

  • A 2-Mb IMC architecture using an emerging VGSOT MRAM device in 22-nm FDSOI technology.
  • supports non-volatile storage, logic operations such as AND, NAND, OR, and NOR, and in-memory dot products for BNNs.
  • A compact 3T1R bit-cell is used with a dual word-line decoder and a separately precharged sense amplifier.
Fig: Logic-in-memory support
Fig: 2-Mb VGSOT MRAM architecture

SARHD: A 6T-SRAM based Side-Channel Attack Resilient Brain-Inspired Hyperdimensional Computing Architecture

Design Specifications

  • Technology: GF 22 FDSOI
  • Memory Technologies: SRAM single-port.
  • Bit-Cell Type: 6 transistor (6T)
  • Memory Capacity: 64 KB
  • Memory Type: Volatile
  • Inference Energy: 297 nJ
  • Accuracy: MNIST 91.26%, FMNIST 87.94%, CIFAR-10 78.52%.

Research Contributions

  • An all-digital 6T-SRAM-based hyperdimensional computing architecture designed for secure and energy-efficient edge intelligence.
  • The design achieves a compact area of 0.3625 mm², consumes 1.79 mW in standby mode and 19.6 mW at 500 MHz, and requires only 297 nJ per inference.
Fig: SARHDC top-level architecture and timing diagram.

A CMOS Compatible Energy Efficient 6T NV-SRAM Based Accelerator Employing Binary Neural Networks in 22 nm FDSOI Technology

Design Specifications

  • Technology: GF 22 FDSOI
  • Memory Technologies: SRAM single-port.
  • Bit-Cell Type: 6 transistor (6T) non-volatile
  • Memory Capacity: 400x200 bit
  • Memory Type: Non-volatile
  • Throughput: 8 TOPS/W
  • Accuracy: MNIST 96.85%

Research Contributions

  • Proposed a CMOS-compatible 6T NV-SRAM based BNN accelerator in 22 nm FDSOI technology for persistent and energy-efficient Edge AI computing.
  • Achieved strong performance with 96.85% MNIST accuracy, 8 TOPS throughput, 200 TOPS/W energy efficiency, and 5 fJ/op operation energy.
Fig: Proposed NV-SRAM cell.
Fig: NV-SRAM cell layout.
Fig: System-level accelerator flow

A 75.47 TOPS/W 4-kb Single-Ended SRAM-Based Compute-in-Memory Architecture Using 16-nm FinFET Technology

Design Specifications

  • Technology: 16 nm 1P9M FinFET
  • Memory Technologies: SRAM-based Compute-In-Memory
  • Bit-Cell Type: 6T single-ended SRAM
  • Memory Capacity: 4 Kb
  • Memory Type: Volatile
  • Throughput: 75.47 TOPS/W

Research Contributions

  • Proposed a 4-kb single-ended 6T SRAM-based Compute-In-Memory architecture in 16 nm FinFET technology for energy-efficient CNN-related operations.
  • Designed a single-ended 6T SRAM cell that removes the direct connection between the complementary bit-line and storage node, reducing energy overhead and improving CIM efficiency.
Fig: 4-kb CIM block diagram
Fig: Post-layout chip view

A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process

Design Specifications

  • Technology: 16 nm 1P11M FinFET CMOS process
  • Memory Technologies: SRAM-based Compute-In-Memory
  • Bit-Cell Type: 6T single-ended SRAM
  • Memory Capacity: 4 Kb
  • Memory Type: Volatile
  • Throughput: 266.7 TOPS/W

Research Contributions

  • Proposed a 4-kb single-ended 6T SRAM-based Compute-In-Memory architecture in 16 nm FinFET CMOS technology for energy-efficient CNN-related computation.
  • Demonstrated high CIM performance with 266.7 TOPS/W energy efficiency, 470.588 GOPS/mm² area efficiency, and support for addition, signed multiplication, and Boolean logic operations at 1 GHz.

References

  1. M. R. Sarkar and C. Y. Yi "NMPHDC: A 12 nm Reconfigurable Multi-port SRAM based Near-Memory Hyperdimensional Computing Architecture," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, doi: 10.1109/JETCAS.2026.3667611.
  2. M. R. Sarkar and C. Y. Yi, "An In-Memory Computing Architecture Utilizing Energy-Efficient VGSOT MRAM Device," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 7, pp. 3258-3262, July 2024, doi: 10.1109/TCSII.2024.3359993.
  3. M. R. Sarkar, S. S. Chowdhury, J. S. Walling and C. Y. Yi, "An In-Memory Power Efficient Computing Architecture with Emerging VGSOT MRAM Device," 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, 2024, pp. 1-5, doi: 10.1109/ISCAS58744.2024.10557835.
  4. M. R. Sarkar, S. S. Chowdhury, G. S. Kumar and C. Y. Yi, "SARHD: A 6T-SRAM based Side-Channel Attack Resilient Brain-Inspired Hyperdimensional Computing Architecture," 2025 IEEE 34th Microelectronics Design & Test Symposium (MDTS), Albany, NY, USA, 2025, pp. 1-6, doi: 10.1109/MDTS64924.2025.11177062.
  5. U. H. Irin, M. R. Sarkar, and C. Y. Yi, "A CMOS Compatible Energy Efficient 6T NV-SRAM Based Accelerator Employing Binary Neural Networks in 22 nm FDSOI Technology," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, doi: 10.1109/JETCAS.2025.3646841.
  6. CY Lo, JS Walling, C. Y. Yi, LC Gunnam, CC Wang, "A 75.47 TOPS/W 4-kb Single-Ended SRAM-Based Compute-in-Memory Architecture Using 16-nm FinFET Technology," Journal of Signal Processing Systems 98 (1), 2026, doi: 10.1007/s11265-026-01998-7.